ITSW 2006 - Call for Papers

CALL FOR PAPERS

Scope

Theme: Living with Imperfection

Growing density has increased the uncertainty of the manufacturing process to the point that it is very difficult to know IC characteristics prior to manufacture. Additional uncertainty is introduced by soft and hard errors accumulated during the lifetime of the IC. Uncertainty can manifest itself directly on the functionality of the chip (i.e. stuck-at, bridging, coupling faults, and etc.) or it can have more subtle impact device parameters such as path delay, clock skew, and leakage.

Testing becomes more critical in this context as a tool to characterize parts in terms of their level of functionality. In order to maintain high yield and durability in the field, defects and variations must be tolerated. Test synthesis, the consideration of test during the synthesis process, is essential to satisfy these strict requirements with low impact on design cost. The workshop will consider all aspects of test and test synthesis including, but not limited, to the following topics:

Register Transfer Level DFT
High-Level/Behavioral Test Synthesis
System-on-a-Chip (SOC) DFT
Memory and Logic BIST
Test Synthesis for Debug and Diagnosis
DFT for Mixed-Signal Circuits
Test Resource Partitioning
Functional Verification
Power and Noise-Aware Test
DFT for At-Speed Test
High-speed I/O test
Reducing the Cost of Test
Design for Manufacturing and Yield
Board and System Test
SER / Concurrent error detection
Test Synthesis for Reconfigurable Logic

For more information, please refer to the web site: http://www.tttc-itsw.org.

Author Information

top

To present recent research results at the workshop, please submit an extended abstract, one to three pages long, in PDF format, to the Program Chair by January 20, 2006 via email. Please include in your abstract the names, affiliations, and full contact information of all authors. Also, please indicate which author will be the speaker if the abstract is accepted for presentation. To support open discussion, no proceedings of the workshop will be published. As in previous years, ITSW will present a BEST Student Paper Award to encourage student participation in the workshop

For general information, contact:

Ian G. Harris, General Chair
Department of Computer Science
University of California Irvine
Irvine, CA 92617? U.S.A.
Email: harris@ics.uci.edu
(ph) 949-824-8842, (fax) 949-824-4056

Submit paper proposals to:

Nilanjan Mukherjee, Program Chair
Design Verification and Test Division
Mentor Graphics Corporation
Willsonville, OR 97070 U.S.A.
Email: nilanjan_mukherjee@mentor.org
(ph) 503-685-1721, (fax)503-685-4729

For more information, visit us on the web at: http://www.tttc-itsw.org

The 13th International Test Synthesis Workshop (ITSW 2006) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

TTTC's Electronic Broadcasting Service
	13th International Test Synthesis Workshop (ITSW 2006) April 9-12, 2006 Fess Parker's Double Tree Resort Santa Barbara, California, USA http://www.tttc-itsw.org

CALL FOR PAPERS
Scope -- Author Information
Scope
Theme: Living with Imperfection Growing density has increased the uncertainty of the manufacturing process to the point that it is very difficult to know IC characteristics prior to manufacture. Additional uncertainty is introduced by soft and hard errors accumulated during the lifetime of the IC. Uncertainty can manifest itself directly on the functionality of the chip (i.e. stuck-at, bridging, coupling faults, and etc.) or it can have more subtle impact device parameters such as path delay, clock skew, and leakage. Testing becomes more critical in this context as a tool to characterize parts in terms of their level of functionality. In order to maintain high yield and durability in the field, defects and variations must be tolerated. Test synthesis, the consideration of test during the synthesis process, is essential to satisfy these strict requirements with low impact on design cost. The workshop will consider all aspects of test and test synthesis including, but not limited, to the following topics: Register Transfer Level DFT High-Level/Behavioral Test Synthesis System-on-a-Chip (SOC) DFT Memory and Logic BIST Test Synthesis for Debug and Diagnosis DFT for Mixed-Signal Circuits Test Resource Partitioning Functional Verification Power and Noise-Aware Test DFT for At-Speed Test High-speed I/O test Reducing the Cost of Test Design for Manufacturing and Yield Board and System Test SER / Concurrent error detection Test Synthesis for Reconfigurable Logic For more information, please refer to the web site: http://www.tttc-itsw.org.
Author Information	top
To present recent research results at the workshop, please submit an extended abstract, one to three pages long, in PDF format, to the Program Chair by January 20, 2006 via email. Please include in your abstract the names, affiliations, and full contact information of all authors. Also, please indicate which author will be the speaker if the abstract is accepted for presentation. To support open discussion, no proceedings of the workshop will be published. As in previous years, ITSW will present a BEST Student Paper Award to encourage student participation in the workshop For general information, contact: Ian G. Harris, General Chair Department of Computer Science University of California Irvine Irvine, CA 92617? U.S.A. Email: harris@ics.uci.edu (ph) 949-824-8842, (fax) 949-824-4056 Submit paper proposals to: Nilanjan Mukherjee, Program Chair Design Verification and Test Division Mentor Graphics Corporation Willsonville, OR 97070 U.S.A. Email: nilanjan_mukherjee@mentor.org (ph) 503-685-1721, (fax)503-685-4729
For more information, visit us on the web at: http://www.tttc-itsw.org
The 13th International Test Synthesis Workshop (ITSW 2006) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).